projects
/
project
/
bcm63xx
/
u-boot.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
dccef2e
)
armv8: fsl-lsch3: enable snoopable sata read and write
author
Tang Yuantian
<
[email protected]
>
Thu, 1 Dec 2016 09:06:58 +0000
(17:06 +0800)
committer
York Sun
<
[email protected]
>
Wed, 18 Jan 2017 17:29:17 +0000
(09:29 -0800)
By default the SATA IP on the ls208Xa SoCs does not generating
coherent/snoopable transactions. This patch enable it in the
sata axicc register.
Signed-off-by: Tang Yuantian <
[email protected]
>
Reviewed-by: York Sun <
[email protected]
>
arch/arm/cpu/armv8/fsl-layerscape/soc.c
patch
|
blob
|
history
diff --git
a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index c0fd1a616d8a06a27e70a2ba2193e46f98a6a2ee..9489f85c642c0f30c18f83a8456af1d6cee4e4b8 100644
(file)
--- a/
arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/
arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@
-213,10
+213,12
@@
int sata_init(void)
ccsr_ahci = (void *)CONFIG_SYS_SATA2;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+ out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ccsr_ahci = (void *)CONFIG_SYS_SATA1;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+ out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
scsi_scan(0);